The present invention relates to semiconductor devices, masks, and processes for forming or designing them and, more particularly, to selective sizing of features to compensate for resist thickness variations.
In the semiconductor manufacture process, the various process steps and their sequence can yield non-planar topographical features of the semiconductor device. The topographical features are necessary in order to provide desired function in the device. The topographical variation caused by the features, however, can present certain problems in the semiconductor manufacturing process and also in operations of the final product semiconductor device.
These problems are particularly encountered in via locations of the device during manufacturing. For example, the exposure energy and procedures to print vias must account for the greatest thicknesses of resist although resist thickness varies. By doing so, overetching or underetching of portions on the same die can occur. This is due to the thicker resist decreasing the etch rates as the aspect ratio of the vias increase. As used herein, aspect ratio of an opening is a ratio of the depth of the opening to the width of the opening.
Resist thickess variations result in via size variations, even within the same die. Thus, a single via exposure produces vias with a range of sizes. This lack of size control can be problematic during manufacturing.
Another problem includes xe2x80x9cside lobingxe2x80x9d when a phase-shifting mask is used. When radiation passes through a phase-shifting mask, a secondary peak in radiation occurs near the edge of the feature being printed in the resist. The resist requires higher levels of radiation to expose the resist at locations where the resist is thicker. However, if the radiation is too high, the secondary peak can exceed the level of energy needed to expose a pattern in the resist. Because these typically occur near the edge of a pattern, it is called xe2x80x9cside lobing.xe2x80x9d If the minimum exposure required for the thicker resist exceeds the maximum exposure before side lobing occurs, undesirable features may be printed.
The problems described above are particularly apparent in trench first, via last (TFVL) manufacturing procedures, which is a process for forming dual-inlaid openings for interconnects or the like, where trenches are formed before via openings. An example of the resist thickness variation is shown in FIG. 1.
FIG. 1 includes an illustration of a cross-sectional view of a prior art semiconductor system 100. The system 100 includes a semiconductor device workpiece 101 having a substrate or insulating layer (a first layer, such as an oxide layer) 102 with trenches 103 and 105. The semiconductor device workpiece 101 includes a second (or resist) layer 104 such as a photoresist layer. The second layer 104 includes openings 106 and 108 to correspond to certain features of the semiconductor device substrate 102. A mask 110 is also included in the system 100 and includes an attenuator (such as a chrome layer) 112 and a substrate (such as glass) 114. The mask 10 also includes openings 116 and 118.
The semiconductor device workpiece 101 is conventional in that it includes a semiconductor device substrate (not shown in full at 102), such as a monocrystalline semiconductor wafer, a semiconductor-on-insulator substrate, or any other substrate suitable for use to form semiconductor devices. As those skilled in the art know and appreciate, the semiconductor device substrate can comprise various layers and configurations, including active, passive, insulative, conductive and other elements, as desired in the particular case.
The resist or second layer 104 is formed over the substrate or insulating layer 102 and within the trenches 103 and 105. Due to the shapes and locations of the trenches, viscosity of the resist layer 104 (when coated), and other fluid mechanical properties, the resist layer 104 is not planar at its uppermost surface and has different thicknesses in the wide trench 105 and the narrow trench 103. The resist layer 104 is patterned to correspond to via locations, which are locations where vias will be formed. With increased trench width, the resist thickness in the trench decreases. For example, the thickness A of the resist 104 in the narrow trench 103 is greater than the thickness B of the resist 104 in the wide trench 105.
Openings 106 and 108 are formed within the resist layer 104 to correspond to the via locations. Before forming openings 106 and 108, the resist layer 104 is significantly thicker where resist opening 106 (e.g. approximately 2.5 microns) will be formed compared to where the resist opening 108 (e.g., approximately 1.7 microns) will be formed. In some technologies, the energy of radiation required to expose the resist layer 104 in forming the opening 106 exceeds the maximum energy before side lobing which will be seen when a phase-shift mask is used.
The resist openings 106 and 108 may have significantly different sizes because of the corresponding differences in resist thicknesses. When the pattern is etched into insulating layer 102, the resulting etched pattern will also have varying sizes, some being larger than desired, some being smaller than desired.
In addition, the different sizes of resist openings 106 and 108 can cause variations in etch rate because of the differences in aspect ratio. The insulating layer 102 will etch more quickly under resist opening 108 because the aspect ratio of resist opening 108 is smaller than the aspect ratio of resist opening 106. The lower aspect ratio allows etchant and etch products to enter and leave the resist opening 108 more easily compared to resist opening 106. The result is that a different amount of time is needed to remove the insulating layer 102 under resist openings 106 and 108.
FIG. 2 is a graphical representation 200 illustrating a size of a feature or dimension in insulating layer 102 as a function of the thickness of the resist in which it is printed. A dashed line 202 represents the bulk effect and is a function of the resist properties. A solid line 204 represents a swing effect variation in feature size and is a function of substrate reflectivity. This curve is generally true for any resist system, but the magnitudes of the linear and sinusoidal components will vary with resist and substrate properties.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with embodiments of the present invention as described herein.